SIF Builder

SIF Builder is a free SIL verification calculator for safety instrumented functions (SIFs). You assemble a safety loop from a sensor, a logic solver and a final element, choose a voting architecture and the diagnostics each subsystem uses, and the tool calculates the loop's PFDavg (low demand) or PFH (high or continuous demand) and the Safety Integrity Level it achieves. It is built for engineers, technicians and students working with IEC 61508 and IEC 61511, and it runs entirely in your browser with no account.

How to use it

1. Pick a preset safety function to start from (conveyor E-stop, overland belt drift, winder slack rope, jaw crusher guarding, silo high level trip or underground gas trip), or configure the loop yourself.
2. Choose the demand mode, low demand (PFDavg) or high/continuous demand (PFH), and set the proof test interval.
3. Open each subsystem. Select a library component, a custom component with your own failure rates, or one exported from FMEDA Workbench. Set the voting architecture (1oo1, 1oo2, 2oo2 or 2oo3) and switch on I/O diagnostics.
4. Inject faults on the wiring diagram, such as a wire break or a short to supply, to see whether an enabled diagnostic catches them.
5. Read the results bar for the loop PFDavg or PFH, the achieved SIL and the factor that limits it. Generate a printable report or copy a link that reopens the same configuration.

Method and assumptions

• Diagnostic coverage. Each diagnostic detects specific fault modes, which sets DC. Then λDD = λD × DC and λDU = λD × (1 − DC).
• Subsystem equations. Simplified PFDavg and PFH equations based on IEC 61508-6 for 1oo1, 1oo2, 2oo2 and 2oo3. Redundant architectures include a common cause β term, and channels built from different components use their own failure rates. The 1oo1 PFDavg also accounts for imperfect proof test coverage over the mission time.
• Loop result. The loop PFDavg or PFH is the sum of the three subsystems, mapped to SIL using the IEC 61508 bands.
• Three limits. The achieved SIL is the lowest of the SIL from the calculated metric, the architectural constraint (Route 1H, from SFF, Type A or B and hardware fault tolerance, when SFF data is available) and each component's systematic capability. Redundancy cannot raise systematic capability.
• Checks. Each subsystem's hardware fault tolerance is checked against an IEC 61511 minimum for the achieved SIL.
• Defaults. β of 5% (sensor), 2% (logic) and 10% (final element), MTTR and MRT of 8 hours, 90% proof test coverage, a 20-year mission time and a one-year proof test interval, all adjustable.
• Data. The component library draws on published safety data from Rockwell Automation, Pilz, SICK, IFM, Turck, Siemens and Finder, plus generic entries. Components without verified data are flagged; check them against the current safety manual.

Questions

Is this a substitute for a formal SIL verification? No. It is an educational tool that calculates hardware PFDavg and PFH only. A complete verification under IEC 61508/61511 also needs software and systematic capability assessment, proof test procedures, management of functional safety and independent review by competent people.

Is my data stored anywhere? Custom components and saved configurations stay in your browser's storage on this device. A share link carries the configuration inside the link itself.